--- nand.py-
+++ nand.py
@@ -357,6 +357,18 @@
 		self.jkff.Q.conn = Pin(self, 'Q')
 		self.jkff.nQ.conn = Pin(self, 'nQ')
 
+class DFF_N(Obj):
+	# D_x, CLK, Q_x
+	def __init__(self, parent, n, name='dff_n', latency=10):
+		Obj.__init__(self, parent, name)
+		self.n = n
+		Pin(self, 'CLK', 'L').conn = Joint(self, 'jt_clk').new_pin()
+		for i in range(n):
+			dff_i = DFF( self, name_i('dff', i), latency )
+			self.jt_clk.new_pin().conn = dff_i.CLK
+			Pin( self, name_i('D', i), 'L' ).conn = dff_i.D
+			dff_i.Q.conn = Pin( self, name_i('Q', i), 'L' )
+
 class COUNTER(Obj):
 	# CLK, out_x
 	def __init__(self, parent, bit_n, name='counter', latency=10):
@@ -426,6 +438,35 @@
 			Pin( self, name_i('sel', i) ).conn = and_i.inp_b
 			and_i.out.conn = Pin( self, name_i('out', i) )
 
+class ANDSetOr(Obj):
+	# inp_x, sel_x, out
+	def __init__(self, parent, n, name='and_set_or', latency=10):
+		Obj.__init__(self, parent, name)
+		ANDSet(self, n, 'and_set', latency)
+		new_pin_n(n, self, 'inp', 0, 'L')
+		conn2_n( n, (self, 'inp', 0), (self.and_set, 'inp', 0) )
+		new_pin_n(n, self, 'sel', 0, 'L')
+		conn2_n( n, (self, 'sel', 0), (self.and_set, 'sel', 0) )
+
+		OR_N(self, n, 'or_n', latency).out.conn = Pin(self, 'out', 'L')
+		conn2_n( n, (self.and_set, 'out', 0), (self.or_n, 'inp', 0) )
+
+class GATE(Obj):
+	# inp_x, en, out_x
+	def __init__(self, parent, n, name='gate', latency=10):
+		Obj.__init__(self, parent, name)
+		self.n = n
+
+		ANDSet(self, n, 'and_set', latency)
+
+		new_pin_n( n, self, 'inp', 0, 'L' )
+		conn2_n( n, (self, 'inp', 0), (self.and_set, 'inp', 0) )
+		new_pin_n( n, self, 'out', 0, 'L' )
+		conn2_n( n, (self.and_set, 'out', 0), (self, 'out', 0) )
+
+		Pin(self, 'en', 'L').conn = Joint(self, 'jt').new_pin()
+		self.jt.new_pin_conn_n( n, self.and_set, 'sel', 0 )
+
 class SELECTOR(Obj):
 	# en, A_x, D_x, out
 	def __init__(self, parent, bit_n, name='selector', latency=10):
@@ -438,13 +479,30 @@
 
 		dn = 1 << bit_n
 		new_pin_n(dn, self, 'D', 0, 'L')
-		ANDSet(self, dn, 'and_set', latency)
-		conn2_n( dn, (self, 'D', 0), (self.and_set, 'inp', 0) )
-		conn2_n( dn, (self.deco, 'out', 0), (self.and_set, 'sel', 0) )
-
-		OR_N(self, dn, 'or_n', latency)
-		conn2_n( dn, (self.and_set, 'out', 0), (self.or_n, 'inp', 0) )
-		self.or_n.out.conn = Pin(self, 'out', 'L')
+		ANDSetOr(self, dn, 'and_set_or', latency)
+		conn2_n( dn, (self, 'D', 0), (self.and_set_or, 'inp', 0) )
+		conn2_n( dn, (self.deco, 'out', 0), (self.and_set_or, 'sel', 0) )
+		self.and_set_or.out.conn = Pin(self, 'out', 'L')
+
+class MUX(Obj):
+	# en, A_x, inp_ax_dx, out_dx
+	def __init__(self, parent, dbit_n, abit_n, name='mux', latency=10):
+		Obj.__init__(self, parent, name)
+		new_pin_n(abit_n, self, 'A', 0, 'L')
+		DECODER(self, abit_n, 'deco', latency)
+		conn2_n( abit_n, (self, 'A', 0), (self.deco, 'inp', 0) )
+		Pin(self, 'en', 'L').conn = self.deco.en
+
+		n = 1 << abit_n
+		Joint_N(self, n, 'jt_deco_out').new_pin_conn( self.deco, 'out', direc='from_targ' )
+
+		for di in range(dbit_n):
+			aso = ANDSetOr( self, n, name_i('and_set_or', di), latency )
+			self.jt_deco_out.new_pin_conn( aso, 'sel', direc='to_targ' )
+			for i in range(n):
+				nm = name_i( name_i('inp', i), di )
+				Pin(self, nm, 'L').conn = getattr( aso, name_i('inp', i) )
+			aso.out.conn = Pin( self, name_i('out', di), 'L' )
 
 class ROM_D1(Obj):
 	# en, A_x, D_0
@@ -469,17 +527,23 @@
 	# en, A_x, D_x
 	def __init__(self, parent, dbit_n, abit_n, dlst=(), name='rom', latency=10):
 		Obj.__init__(self, parent, name)
-		self.n = dbit_n
-		Pin(self, 'en', 'L').conn = Joint(self, 'jt_en').new_pin()
+
+		MUX(self, dbit_n, abit_n, 'mux', latency)
+		Pin(self, 'en', 'L').conn = self.mux.en
 		new_pin_n(abit_n, self, 'A', 0, 'L')
-		Joint_N(self, abit_n, 'jt_n_A').new_pin_conn(self, 'A', 0, abit_n, 'from_targ')
+		conn2_n( abit_n, (self, 'A', 0), (self.mux, 'A', 0) )
+		new_pin_n(dbit_n, self, 'D', 0, 'L')
+		conn2_n( dbit_n, (self.mux, 'out', 0), (self, 'D', 0) )
+
+		f = lambda s, v: s + [ (v >> di) & 1 for di in range(dbit_n) ]
+		lst = reduce(f, dlst, [])
+		dbgout(lst)
 
-		for i in range(dbit_n):
-			dlst_i = [ (d >> i) & 1 for d in dlst ]
-			rom_b = ROM_D1(self, abit_n, dlst_i, name_i('rom_b', i), latency)
-			self.jt_en.new_pin().conn = rom_b.en
-			self.jt_n_A.new_pin_conn(rom_b, 'A', 0, abit_n, 'to_targ')
-			rom_b.D_0.conn = Pin( self, name_i('D', i), 'L' )
+		# as late as possible, for data enque
+		n = 1 << abit_n
+		PinSet(self, n * dbit_n, lst, 'pin_set')
+		for i in range(n):
+			conn2_n( dbit_n, (self.pin_set, 'p', i * dbit_n), ( self.mux, name_i('inp', i), 0 ) )
 
 class CLK(Obj):
 	# en, out