--- nand.py-
+++ nand.py
@@ -369,6 +369,28 @@
 			Pin( self, name_i('inp', i), 'L' ).conn = dff_i.D
 			dff_i.Q.conn = Pin( self, name_i('out', i), 'L' )
 
+class LATCH_N(Obj):
+	# inp_dx, CLK, sel_x, out_x_dx
+	def __init__(self, parent, n, dbit_n, name='latch_n', latency=10):
+		Obj.__init__(self, parent, name)
+
+		JointANDSet(self, n, 'jas', latency)
+		Pin(self, 'CLK', 'L').conn = self.jas.inp
+		new_pin_n(n, self, 'sel', 0, 'L')
+		conn2_n( n, (self, 'sel', 0), (self.jas, 'sel', 0) )
+
+		new_pin_n(dbit_n, self, 'inp', 0, 'L')
+		Joint_N(self, dbit_n, 'jt_inp', latency)
+		self.jt_inp.new_pin_conn(self, 'inp', direc='from_targ')
+
+		for i in range(n):
+			lt = LATCH(self, dbit_n, name_i('latch', i), latency)
+			getattr( self.jas, name_i('out', i) ).conn = lt.CLK
+			self.jt_inp.new_pin_conn(lt, 'inp', direc='to_targ')
+
+			new_pin_n( dbit_n, self, name_i('out', i), 0, 'L' )
+			conn2_n( dbit_n, (lt, 'out', 0), (self, name_i('out', i), 0) )
+
 class COUNTER(Obj):
 	# CLK, out_x
 	def __init__(self, parent, bit_n, name='counter', latency=10):
@@ -451,6 +473,20 @@
 		OR_N(self, n, 'or_n', latency).out.conn = Pin(self, 'out', 'L')
 		conn2_n( n, (self.and_set, 'out', 0), (self.or_n, 'inp', 0) )
 
+class JointANDSet(Obj):
+	# inp, sel_x, out_x
+	def __init__(self, parent, n, name='joint_and_set', latency=10):
+		Obj.__init__(self, parent, name)
+		Pin(self, 'inp', 'L').conn = Joint(self, 'jt').new_pin()
+
+		ANDSet(self, n, 'and_set', latency)
+		self.jt.new_pin_conn_n( n, self.and_set, 'inp', 0 )
+
+		new_pin_n(n, self, 'sel', 0, 'L')
+		conn2_n( n, (self, 'sel', 0), (self.and_set, 'sel', 0) )
+		new_pin_n(n, self, 'out', 0, 'L')
+		conn2_n( n, (self.and_set, 'out', 0), (self, 'out', 0) )
+
 class GATE(Obj):
 	# inp_x, en, out_x
 	def __init__(self, parent, n, name='gate', latency=10):
@@ -485,7 +521,7 @@
 		self.and_set_or.out.conn = Pin(self, 'out', 'L')
 
 class MUX(Obj):
-	# en, A_x, inp_ax_dx, out_dx
+	# en, A_x, inp_ax_dx, out_dx, deco_out_ax
 	def __init__(self, parent, dbit_n, abit_n, name='mux', latency=10):
 		Obj.__init__(self, parent, name)
 		new_pin_n(abit_n, self, 'A', 0, 'L')
@@ -496,6 +532,9 @@
 		n = 1 << abit_n
 		Joint_N(self, n, 'jt_deco_out').new_pin_conn( self.deco, 'out', direc='from_targ' )
 
+		new_pin_n(n, self, 'deco_out', 0, 'L')
+		self.jt_deco_out.new_pin_conn( self, 'deco_out', direc='to_targ' )
+
 		for di in range(dbit_n):
 			aso = ANDSetOr( self, n, name_i('and_set_or', di), latency )
 			self.jt_deco_out.new_pin_conn( aso, 'sel', direc='to_targ' )
@@ -545,6 +584,28 @@
 		for i in range(n):
 			conn2_n( dbit_n, (self.pin_set, 'p', i * dbit_n), ( self.mux, name_i('inp', i), 0 ) )
 
+class RAM(Obj):
+	# en, CLK, A_x, D_x
+	def __init__(self, parent, dbit_n, abit_n, name='ram', latency=10):
+		Obj.__init__(self, parent, name)
+
+		n = 1 << abit_n
+		LATCH_N(self, n, dbit_n, 'latch_n', latency)
+		Pin(self, 'CLK', 'L').conn = self.latch_n.CLK
+		new_pin_n( dbit_n, self, 'inp', 0, 'L' )
+		conn2_n( dbit_n, (self, 'inp', 0), (self.latch_n, 'inp', 0) )
+
+		MUX(self, dbit_n, abit_n, 'mux', latency)
+		Pin(self, 'en', 'L').conn = self.mux.en
+		new_pin_n( abit_n, self, 'A', 0, 'L' )
+		conn2_n( abit_n, (self, 'A', 0), (self.mux, 'A', 0) )
+		new_pin_n( dbit_n, self, 'out', 0, 'L' )
+		conn2_n( dbit_n, (self.mux, 'out', 0), (self, 'out', 0) )
+
+		conn2_n( n, (self.mux, 'deco_out', 0), (self.latch_n, 'sel', 0) )
+		for i in range(n):
+			conn2_n( dbit_n, (self.latch_n, name_i('out', i), 0), (self.mux, name_i('inp', i), 0) )
+
 class CLK(Obj):
 	# en, out, Q, nQ
 	def __init__(self, parent, hz=1.0, name='clk', pos=(0,0), lamp_name=None, latency=10):