--- nand.py-
+++ nand.py
@@ -584,6 +584,37 @@
 		for i in range(n):
 			conn2_n( dbit_n, (self.pin_set, 'p', i * dbit_n), ( self.mux, name_i('inp', i), 0 ) )
 
+class ROM_SEQ(Obj):
+	# en, out_x, Q, nQ
+	def __init__(self, parent, dbit_n, abit_n, dlst=(), name='rom_seq', hz=1.0, pos=(0,0), lamp_name=None, latency=10):
+		Obj.__init__(self, parent, name, None, pos)
+		Pin(self, 'en', 'L').conn = Joint(self, 'jt_en').new_pin()
+
+		CLK(self, hz, 'clk', (0,0), lamp_name, latency)
+		self.jt_en.new_pin().conn = self.clk.en
+		self.clk.Q.conn = Joint(self, 'jt_Q').new_pin()
+		self.jt_Q.new_pin().conn = Pin(self, 'Q', 'L')
+		self.clk.nQ.conn = Joint(self, 'jt_nQ').new_pin()
+		self.jt_nQ.new_pin().conn = Pin(self, 'nQ', 'L')
+
+		COUNTER(self, abit_n, 'counter', latency)
+		self.jt_Q.new_pin().conn = self.counter.CLK
+
+		LATCH(self, abit_n, 'latch_a', latency)
+		conn2_n( abit_n, (self.counter, 'out', 0), (self.latch_a, 'inp', 0) )
+		self.jt_nQ.new_pin().conn = self.latch_a.CLK
+
+		ROM(self, dbit_n, abit_n, dlst, 'rom', latency)
+		conn2_n( abit_n, (self.latch_a, 'out', 0), (self.rom, 'A', 0) )
+		self.jt_en.new_pin().conn = self.rom.en
+
+		LATCH(self, dbit_n, 'latch_d', latency)
+		conn2_n( dbit_n, (self.rom, 'D', 0), (self.latch_d, 'inp', 0) )
+		self.jt_Q.new_pin().conn = self.latch_d.CLK
+
+		new_pin_n(dbit_n, self, 'out', 0, 'L')
+		conn2_n( dbit_n, (self.latch_d, 'out', 0), (self, 'out', 0) )
+
 class RAM(Obj):
 	# en, CLK, A_x, D_x
 	def __init__(self, parent, dbit_n, abit_n, name='ram', latency=10):
@@ -606,6 +637,50 @@
 		for i in range(n):
 			conn2_n( dbit_n, (self.latch_n, name_i('out', i), 0), (self.mux, name_i('inp', i), 0) )
 
+class RAM_TEST_4(Obj):
+	# en
+	def __init__(self, parent, abit_n, dlst=(), name='ram_test_4', hz=1.0, pos=(0,0), latency=10):
+		Obj.__init__(self, parent, name, None, pos)
+
+		Pin(self, 'en', 'L').conn = Joint(self, 'jt_en').new_pin()
+
+		(x,y) = (0,0)
+		ROM_SEQ(self, 8, abit_n, dlst, 'rom_seq', hz, (x,y), 'CLK', latency)
+		self.jt_en.new_pin().conn = self.rom_seq.en
+		x += 10
+		Joint_N(self, 4, 'jt_d', None, (x,y), ('y',1), 'D')
+		self.jt_d.new_pin_conn(self.rom_seq, 'out', direc='from_targ')
+		y += 4+1
+		Joint_N(self, 3, 'jt_a', None, (x,y), ('y',1), 'A')
+		self.jt_a.new_pin_conn(self.rom_seq, 'out', 4, direc='from_targ')
+		y += 3+1
+		self.rom_seq.out_7.conn = Joint(self, 'jt_ctl', None, (x,y), 'CTL').new_pin()
+		self.rom_seq.nQ.conn = Joint(self, 'jt_nQ').new_pin()
+		y_bak = y
+		
+		RAM(self, 4, 3, 'ram', latency)
+		self.jt_en.new_pin().conn = self.ram.en
+		self.jt_d.new_pin_conn(self.ram, 'inp', direc='to_targ')
+		self.jt_a.new_pin_conn(self.ram, 'A', direc='to_targ')
+
+		x += 10
+		y = 0
+		x_bak = x
+		Joint_N(self, 4, 'jt_ram_out', None, (x,y), ('y',1), 'O')
+		self.jt_ram_out.new_pin_conn(self.ram, 'out', direc='from_targ')
+
+		DECODER_Lamp_7seg(self, 'deco_lamp_7seg', latency, (40,0))
+		self.jt_en.new_pin().conn = self.deco_lamp_7seg.en
+		self.jt_ram_out.new_pin_conn(self.deco_lamp_7seg, 'inp', direc='to_targ')
+
+		x = x_bak
+		y = y_bak
+		AND(self, 'and_w', latency)
+		self.jt_ctl.new_pin().conn = self.and_w.inp_a
+		self.jt_nQ.new_pin().conn = self.and_w.inp_b
+		self.and_w.out.conn = Joint(self, 'jt_wrt', None, (x,y), 'W').new_pin()
+		self.jt_wrt.new_pin().conn = self.ram.CLK
+
 class CLK(Obj):
 	# en, out, Q, nQ
 	def __init__(self, parent, hz=1.0, name='clk', pos=(0,0), lamp_name=None, latency=10):